A CMOS Clock and Data Recovery Circuit with a Half-Rate Three-State Phase Detector

A clock and data recovery (CDR) circuit using a new halfrate wide-range phase detection technique has been developed. Unlike the conventional three-state phase detectors, the proposed detector is applicable to the Non-Return-to-Zero (NRZ) data stream and also has low jitter and wide capture range characteristics. The CDR circuit was implemented in a 0.35-μm N-well CMOS technique. Experimental results demonstrate that it can achieve the peak-to-peak jitter of the recovered clock and the retimed data about 120 ps and 170 ps, respectively, while operating at the input data rate of 1 Gb/s. The total power dissipation of the CDR is 64.8 mW for the supply 3 V. key words: phase-locked loop, phase synchronization, clock and data recovery, phase detector